Dynamic Random Access Memories (DRAMs) have long been a popular choice for use as main memory in computer systems, especially for low cost computer systems such as personal computers (PCs) and workstations. This is largely because DRAMs use a simple memory cell geometry that permits implementation of large memory arrays at minimum cost and power consumption on a single semiconductor chip.
However, as processor speeds increase beyond a certain point, DRAM technology has been found to have significant access time incompatibilities. This is because the switching speed within a conventional DRAM memory cell is not as fast as the switching speeds now common in central processing units (CPUs). As a result, when using high speed processors with conventional DRAMs, the processor must frequently wait for memory accesses to be completed.
DRAMs support a type of access known as page mode wherein adjacent locations can be accessed sequentially at high speed. This feature is particularly effective in memory intensive applications in which it is common for groups of memory locations to be read or written in sequential order.
In addition, in a DRAM, all of the cells in a given group of memory locations, or a so-called "row," are activated at the same time. Multiple read or write operations can thus be performed with various cells within the row, but only while it is active. If a new access is to be made to a different row, a precharge operation must be completed to close the presently active row prior to accessing a different row. Therefore, a delay equal to the precharge time is experienced whenever a different row must be accessed on a subsequent transaction. However, the precharge operation is only necessary if the row address changes; if the row address does not change on the subsequent access, the precharge operation has been unnecessarily executed and the device unnecessarily placed in an idle state.
A new type of DRAM, called a synchronous DRAM (SDRAM), is rapidly becoming a popular option for use as main memory. SDRAMs use the same memory cell technology as DRAMs, which is to say they use a single complimentary metal-oxide-semiconductor (CMOS) transistor switch coupled to a storage capacitor. There are, however, several differences in the internal structure of an SDRAM that provide certain speed advantages.
The first such difference is that the operation of an SDRAM is synchronous. In particular, read/write access and refresh cycles occur synchronously with a master clock signal. Therefore, a computer system can be designed using SDRAMs, knowing the exact timing of events within the memory.
Second, being synchronous, SDRAM arrays can be split into two or more independent memory banks, and two or more rows can therefore be active simultaneously, with one open row per independent bank. If a computer system is designed to support interleaved accesses to multiple rows, SDRAMs make it possible to complete these accesses without intervening precharge operations, provided that the rows to be accessed are all in separate SDRAM banks.